Publications

* denotes equal contribution

2027

• [ASPDAC] Shuao Jia, Zichao Ling, Chen Bai, Bei Yu, Kang Zhao, Jianwang Zhai. “FADiff: Fusion-Aware Differentiable Optimization for DNN Scheduling on Tensor Accelerators”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Jan. 25–28, 2027.
• [ASPDAC] Debin Cao, Kanglin Tian, Ze Hao, Yi Huang, Bei Yu, Jianwang Zhai, Kang Zhao. “Thermal-Aware Chiplet Placement Integrating Evolutionary Reinforcement Learning and Monte Carlo Tree Search”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Jan. 25–28, 2027.
• [ASPDAC] Hao Luo, Zhenghao Chen, Kanglin Tian, Kang Zhao, Jianwang Zhai. “Opening the Black Box: A Self-Correcting LLM Agent for EDA Toolchains Based on Source-Code Analysis”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Jan. 25–28, 2027.
• [ASPDAC] Zichao Ling, Chen Bai, Kang Zhao, Jianwang Zhai. “UACC: A Chiplet-Based Auxiliary Cache for Cost-Effective Performance Scaling in Multicore Processors”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Jan. 25–28, 2027.
• [ASPDAC] Yijun Chen, Chunyan Pei, Jianwang Zhai, Siwen Song, Huiyao Weng, Jian Shen, Kang Zhao, Wenjian Yu. “Timing-Aware Routing and Heterogeneous TDM Assignment for Multi-Level FPGA-Based Emulation Systems”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Jan. 25–28, 2027.
• [ASPDAC] Minghao Dong, Junfeng Cai, Jianwang Zhai, Fei Zhao, Jiaji He, Kang Zhao, Yongqiang Lyu. “PARFuzzer: Path-Aware RTL Fuzzing with Controlled BTB Conflict Injection for Branch-Predictor Security Validation”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Jan. 25–28, 2027.

2026

• [ICCD] Lin Li, Kanglin Tian, Jianwang Zhai, and Kang Zhao. “PBDR-FP: Plateau-Guided Bottleneck Repair for Feasibility Recovery in Fixed-Outline 3D Floorplanning”, IEEE International Conference on Computer Design (ICCD), 2026.
• [ICCD] Ze Hao, Jianwang Zhai, Ding Gong, Kang Zhao, and Wenjian Yu, “SwitchSim: A SPICE-like Simulator for Switching Circuits Based on State-driven Unified Branch Stamps”, IEEE International Conference on Computer Design (ICCD), 2026. [pdf]
• [ICCAD] Ze Hao, Yu Zhang, Haoxuan Song, Tianyu Liang, Yijun Chen, Jianwang Zhai, and Kang Zhao. “QuantizeHeat: Generalizable Thermal Prediction for 2.5D Chiplets via Thermal-Aware Discrete Latent Space Mapping”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2026.
• [ICCAD] Shuao Jia, Zichao Ling, Chen Bai, Jianwang Zhai, and Kang Zhao. “Tri-Stack-PIM: A Heterogeneous Multi-Die 3D-Integrated Processing-in-Memory Architecture for Efficient LLM Inference”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2026.
• [ICCAD] Yuheng Huang, Yuhan Qin, Yuan Pu, Zhaotan Lin, Yuntao Nie, Zhuolun He, Jianwang Zhai, Kang Zhao, and Bei Yu. “A Multi-Granularity Retrieval Augmented Generation Framework for EDA Tasks Leveraging Knowledge Graph”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2026.
• [ICCAD] Xingyu Qin*, Guande Dong*, Chenshen Lin, Jianwang Zhai, and Kang Zhao. “ChoMerge: Dual-Output LUT Optimization via LUT-Level Choice Network and Routing-Aware Merging”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2026. (*Equal contribution)
• [ISCAS] Donghao Guo, Zhe Lin, Jianwang Zhai, Kang Zhao, “Performance Pragma-Based Design Space Pruning and Exploration for High-Level Synthesis”, IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, China, May. 24–27, 2026. [pdf] [slides]
• [GLSVLSI] Yujie Zhang, Xiao Yang, Kang Zhao, and Jianwang Zhai. “Etch-Explorer: A Robust Bayesian Optimization Framework for Stringent Constrained Plasma Etching”, Proc. of the Great Lakes Symposium on VLSI 2026 (GLSVLSI’26), Canandaigua, June 2026. [pdf] [slides]
• [GLSVLSI] Hengyuan Zhang*, Kanglin Tian*, Zirui Li, Xiuli Fu, Jianwang Zhai, Kang Zhao. “Structural Timing-Aware Circuit Partitioning with Feasibility Constraints for Multi-Chiplet Design”, Proc. of the Great Lakes Symposium on VLSI 2026 (GLSVLSI’26), Canandaigua, NY, USA, June 2026. [pdf] [slides]
• [TCAD] Kang Yang, Jianwang Zhai, Liuyu Xiang, Kang Zhao, Wei Li, Ming Lei, Zhaofeng He. “DrlGoFPGA 2.0: FPGA Global Placement Based on Multi-Agent Graph Transformers and Nonlinear Placement Co-Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, May 2026. [pdf]
• [TCAD] Kai Shi, Zhe Lin, Xinya Luan, Jianwang Zhai, Kang Zhao. “FVSpGEMM: A Comprehensive Framework for Exploiting Versal ACAP in High-Performance SpGEMM Acceleration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jun. 2026. [pdf]
• [TCAD] Xinya Luan, Zhe Lin, Kai Shi, Jianwang Zhai, Kang Zhao. “HeteroSVD+: Efficient SVD Accelerator on Versal ACAP with Hardware-Aware Design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2026.
• [TRETS] Xinya Luan, Zhe Lin, Kai Shi, Liyang Dou, Jianwang Zhai, Kang Zhao. “AIEAnalyzer: An Analytical Framework for Versal AI Engine Performance Analysis” ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2026.
• [DAC] Feng Guo*, Yueyue Xi*, Jingyu Jia, Jiawei Liu, Tianshu Hou, Yuyang Ye, Jianwang Zhai, Kang Zhao and Chuan Shi. “GEMIR: Graph-Based Joint Modeling of Electromigration and IR Drop for Power Grid”, ACM/IEEE Proceedings Design Automation Conference (DAC), Long Beach, CA, USA, 2026.
• [DAC] Zixuan Li*, Kanglin Tian*, Fan Hu, Zirui Li, Xinyue Wu, Hengyuan Zhang, Shixin Chen, Jianwang Zhai, Xinfei Guo and Kang Zhao. “ChiPlanner: Physically-Aware and Timing-Driven Design Planner for 2.5D Multi-Chiplet Systems”, ACM/IEEE Proceedings Design Automation Conference (DAC), Long Beach, CA, USA, 2026.
• [DATE] Yingxin Zeng, Binghao Cheng, Jianwang Zhai, Kang Zhao, and Zhe Lin, “AutoShrink: Adaptive Search Space Shrinkage for Large-Scale Pareto Optimization of HLS Designs,” in IEEE/ACM Proceedings Design, Automation & Test in Europe Conference (DATE), Verona, Italy, April 2026. [pdf] [slides]
• [DATE] Zhenghao Chen, Yuan Pu, Hairuo Han, Yuntao Nie, Jiajun Qin, Yuhan Qin, Tairu Qiu, Zhuolun He, Jianwang Zhai, Bei Yu and Kang Zhao. “MAEDA: An LLM-Powered Multi-Agent Evaluation Framework for EDA Tool Documentation QA”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Verona, Italy, 2026. [pdf] [slides] [poster]
• [DATE] Xingyu Qin, Guande Dong, Jianwang Zhai, Kang Zhao. “DynaOpt: A Heterogeneous Logic Optimization Framework with Dynamic Sequence Generation”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Verona, Italy, 2026. [pdf] [slides] [poster]
• [ASPDAC] Zibo Hu, Zhe Lin, Renjing Hou, Xingyu Qin, Jianwang Zhai, Kang Zhao. “HLS-Timer: Fine-Grained Path-Level Timing Estimation for High-Level Synthesis”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Hong Kong, Jan 2026.[pdf] [slides]
• [ASPDAC] Yijun Chen*, Haoyuan Li*, Chunyan Pei, Jianwang Zhai, Kang Zhao and Wenjian Yu. “Timing-aware optimization of die-level routing and TDM assignment for multi-FPGA systems”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Hong Kong, Jan 2026. (*Equal contribution)[pdf] [slides]

2025

• [TCAD] Sen Yan, Kuangxun Huang, Kang Zhao, Zhe Lin. “Accurate, Efficient and Scalable Power Modeling for FPGA HLS,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Dec 2025. [pdf]
• [FPT] Liyang Dou, Zhe Lin, Kai Shi, Xinya Luan, and Kang Zhao. “An End-to-End Tool Flow with Intrinsic-Level Kernel Optimization on Versal ACAP”, IEEE International Conference on Field-Programmable Technology(FPT), Shanghai, Dec 2025. [pdf] [slides]
• [GLSVLSI] Zichao Ling, Lin Li, Yi Huang, Yixin Xuan, Jianwang Zhai, Kang Zhao. “AuxiliarySRAM: Exploring Elastic On-Chip Memory in 2.5D Chiplet Systems Design”, Proc. of the Great Lakes Symposium on VLSI 2025 (GLSVLSI’25), New Orleans, June 2025. [pdf] [slides]
• [TCAS-I] Kang Yang, Jianwang Zhai, Liuyu Xiang, Zixi Huang, Dan Wu, Yida Wang, Kang Zhao, Ming Lei, and Zhaofeng He. “DrlGoFPGA: FPGA Global Placement Considering Input-Output Buffer Based on Deep Reinforcement Learning and Gradient Optimization,” IEEE Transactions on Circuits and Systems—I: Regular Papers, May 2025. [pdf]
• [DAC] Xinya Luan, Zhe Lin, Kai Shi, Jianwang Zhai, Kang Zhao. “HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun 2025. [pdf] [slides]
• [DAC] Kai Shi, Zhe Lin, Xinya Luan, Jianwang Zhai, Kang Zhao. “VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun 2025. [pdf] [slides]
• [DAC] Feng Guo, Yueyue Xi, Jianwang Zhai, Jingyu Jia, Jiawei Liu, Kang Zhao, Chuan Shi. “IRGNN: A Graph-based Framework Integrating Numerical Solution and Point Cloud for Static IR Drop Prediction”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun 2025. [pdf] [slides]
• [ASICON] Maoshuo He*, Renjing Hou*, Zirui Li, and Kang Zhao. “Snow Ablation Optimizer Accelerator Based on High Level Synthesis”, IEEE International Conference on ASIC (ASICON), Kunming, Oct 2025. [pdf]
• [ISEDA] Luming Wang, Fangli Liu, Zichao Ling, Zheqin Cao, Yixin Xuan, Jianwang Zhai, and Kang Zhao. “Simulation and Exploration for Multi-Chiplet Systems using Open-Source Tools and Heuristic Algorithm,” Proc. International Symposium on Electronic Design Automation (ISEDA), Hong Kong, May 2025. [pdf] [poster]
• [ISEDA] Yang Xiao, Xingyu Qin, Yujie Zhang, Jianwang Zhai, Kang Zhao. “Multi-Objective Bayesian Target Interval Optimization for Semiconductor Process Parameters”, Proc. International Symposium on Electronic Design Automation (ISEDA), Hong Kong, May 2025. [pdf] [slides]
• [ISCAS] Zixuan Li*, Kanglin Tian*, Jianwang Zhai, Zirui Li, Kang Zhao. “HieRFP: A Hierarchical Recognition and Floorplanning Framework for Reusable Modules”, IEEE International Symposium on Circuits and Systems (ISCAS), London, UK, May 2025. (*Equal contribution)
• [DATE] Feng Guo, Jianwang Zhai, Jingyu Jia, Jiawei Liu, Kang Zhao, Bei Yu, Chuan Shi. “IR-Fusion: A Fusion Framework for Static IR Drop Analysis Combining Numerical Solution and Machine Learning”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Lyon, France, 2025. [pdf] [slides]
• [ASPDAC] Guande Dong, Jianwang Zhai, Hongtao Cheng, Xiao Yang, Chuan Shi, Kang Zhao. “PIRLLS: Pretraining with Imitation and RL Finetuning for Logic Synthesis”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Jan 2025. [pdf] [slides]
• [ASPDAC] Zirui Li*, Kanglin Tian*, Jianwang Zhai, Zixuan Li, Shixiong Kai, Siyuan Xu, Bei Yu, Kang Zhao. “FTAFP: A Feedthrough-Aware Floorplanner for Hierarchical Design of Large-Scale SoCs”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Jan 2025. [pdf] [slides] (*Equal contribution)

2024

• [DATE] Jingyu Jia, Jianwang Zhai, Kang Zhao. “Fast Estimation for Electromigration Nucleation Time Based on Random Activation Energy Model”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Valencia, Spain, March 2024. [pdf] [slides]
• [DATE] Enxin Yi, Yiru Duan, Yinuo Bai, Kang Zhao, Zhou Jin and Weifeng Liu. “Cuper: Customized Dataflow and Perceptual Decoding for Sparse Matrix-Vector Multiplication on HBM-Equipped FPGAs,” 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, March 2024, pp. 1-6. [pdf] [slides]
• [GLSVLSI] Feng Guo*, Jiawei Liu*, Jianwang Zhai, Jingyu Jia, Kang Zhao, Chuan Shi. “PGAU: Static IR Drop Analysis for Power Grid using Attention U-Net Architecture and Label Distribution Smoothing”, ACM Great Lakes Symposium on VLSI (GLSVLSI), FL, USA, Jun 2024. [pdf] [slides] (*Equal contribution)
• [ISCAS] Zirui Li, Jianwang Zhai, Zixuan Li, Zhongdong Qi, Kang Zhao. “Effective Resource Model and Cost Scheme for Maze Routing in 3D Global Routing”, IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, May 2024. [pdf] [poster]
• [ISEDA] Renjing Hou, Jianwang Zhai, Yajun Wang, Zhe Lin, Kang Zhao. “Array Partitioning Method for Streaming Dataflow Optimization in High-level Synthesis”, International Symposium of Electronics Design Automation (ISEDA), Xi’an, China, May 2024. [pdf] [slides]
• [ISEDA] Chen Yang, Renjing Hou, Qirui Yang, Wenjian Yu and Kang Zhao. “Automated Python-to-RTL Transformation and Optimization for Neural Network Acceleration,” International Symposium of Electronics Design Automation (ISEDA), Xi’an, China, 2024, pp. 253-258. [pdf] [slides]
• [JCAD] 田康林, 赵康. “基于CNFET 电路段内关键门的全局布局算法”. 计算机辅助设计与图形学学报, 2024, 36(3): 464-472. [pdf]
• [JCRD] 翟建旺, 凌梓超, 白晨, 赵康, 余备. “机器学习辅助微架构功耗建模和设计空间探索综述”. 计算机研究与发展, 2024, 61(6): 1351-1369. [pdf]
• [CSTIC] Heng Zi, Kang Zhao, Wei Zhang. “Designing and Accelerating Spiking Neural Network Based on High-Level Synthesis”, Conference of Science and Technology for Integrated Circuits (CSTIC), Shanghai, March 2024. [pdf]

2023

• [ACM TRETS] Kang Zhao, Yuchun Ma, Ruining He, Jixing Zhang, Ning Xu, and Jinian Bian. Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow. ACM Transactions on Reconfigurable Technology and Systems, Vol 16, Issue 2: 1-24. April 2023. [pdf]
• [ISEDA] Qirui Yang, Kang Zhao, Wenjian Yu, Yun Shao, Yong Xiao. A Resource Sharing Approach for Logic Synthesis Based on Monte Carlo Tree Search,” 2023 International Symposium of Electronics Design Automation (ISEDA), Nanjing, 2023, pp. 190-194. [pdf]

2010-2022

• [16] [TVLSI] Kang Zhao, Wenbo Shen. Parallel Stimulus Generation Based on Model Checking for Coherence Protocol Verification. IEEE Trans VLSI Systems, Volume: 23, Issue: 99, ISSN: 1063-8210, Dec 2015, pp 1063-8210. [pdf]
• [15] [ASPDAC] Jianlei Yang, Liwei Ma, Kang Zhao, Yici Cai, Tin-fook Ngai. Early Stage Real-Time SoC Power Estimation Using RTL Instrumentation. Asia and South Pacific Design Automation Conference (ASP-DAC), 2015. [pdf]
• [14] [ICCAD] Ruining He, Yuchun Ma, Kang Zhao, Jinian Bian. “ISBA: An Independent Set-Based Algorithm for Automated Partial Reconfiguration Module Generation”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2012, pp.500-507. [pdf]
• [13] [IEICE] Kang Zhao, Jinian Bian. Pruning-Based Trace Signal Selection Algorithm for Data Acquisition in Post-Silicon Validation. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences. Vol.E95-A (No.6), 2012: 1030-1040.
• [12] [ASPDAC] Kang Zhao, Jinian Bian. Pruning-based Trace Signal Selection Algorithm. Asia and South Pacific Design Automation Conference (ASP-DAC). Yokohama, 2011. [pdf] [slides]
• [11] [IEICE] Kang Zhao, Jinian Bian. Processor Accelerator Customization through DFG Exploration. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, Vol.E94-A (No.7), 2011: 1540-1552.
• [10] [APCCAS] Kang Zhao, Jinian Bian. Peeling Algorithm for Custom Instruction Identification. IEEE Asia Pacific Conference on Circuits and Systems. Kuala Lumpur, Malaysia, Dec 2010. [pdf] [slides]
• [9] [CSCWD] Kang Zhao, Jinian Bian. Instruction-level hardware/software partition through DFG exploration. International Conference on CSCWD. Switzerland, June 2011. [pdf]

Before 2010

• [8] [IEICE] Kang Zhao, Jinian Bian, and et al. Pipeline-based Partition Exploration for Heterogeneous Multiprocessor Synthesis. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, Vol.E92-A (No.9), 2009: 2283-2294.
• [7] [IEICE] Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto. Exploring Partitions based on Search Space Smoothing for Heterogeneous Multiprocessor System. IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, Vol.E91-A (No.9), 2008: 2456-2464.
• [6] [IEICE] Kang Zhao, Jinian Bian, et al. Fast Custom Instruction Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences, Vol.E91-A (No.6), June 2008: 1478-1487.
• [5] [GLSVLSI] Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto. HyMacs: Hybrid Memory Access Optimization based on Custom-instruction Scheduling. Proceedings of ACM Great Lakes Symposium on VLSI, Orlando, USA, May 2008: 89-94. [pdf] [slides]
• [4] [ISQED] Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto. Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration. Proceedings of International Symposium on Quality Electronic Design, San Jose, CA, March 2008: 321-324. [pdf]
• [3] [JCAD] 赵康, 边计年, 董社勤. 基于集束式整数线性规划模型的专用指令集自动定制. 计算机辅助设计与图形学学报(JCAD), 19(10), 2007.10: 1229-1234. (EI) [pdf]
• [2] [CSCWD] Kang Zhao, Jinian Bian, Sheqin Dong. A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. Proc. International Conference on Computer Supported Cooperative Work in Design, Melbourne, 2007. [pdf]
• [1] [APCCAS] Kang Zhao and Jinian Bian. A Clustering ILP Model for Fast Instruction Selection in Embedded Applicated Specific Processor Design. Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Singapore, December 2006: 1160-1163. [pdf]